
Nick Flaherty
Editor-in-Chief and Power Editor at E&E News
Technology Editor at E-Mobility Engineering
Technology journalist, editor in chief and power editor @eeNewsEurope, tech editor at Uncrewed Systems Technology mag and e-mobility engineering
Articles
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6 days ago |
ecinews.fr | Nick Flaherty |A Delapalisse
Actualités économiques | 18 avril 2025 Par Nick Flaherty, A Delapalisse La base de données CVE (Common Vulnerability and Exposures), actuellement gérée par l’entreprise de cybersécurité MITRE, détaille les vulnérabilités potentielles du matériel et des logiciels pour les systèmes du monde entier au cours des 25 dernières années.
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6 days ago |
eenewseurope.com | Nick Flaherty
Swiss industrial equipment giant ABB is to spin out its robotics division. With 7,000 employees and 2024 revenues of $2.3bn, this would create the world’s second largest robotics company after Mitsubishi Electric Automation. Fanuc in Japan is third largest in revenue with $1.38bn. To do this, the company is launching a process to propose this at its 2026 Annual General Meeting.
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6 days ago |
eenewseurope.com | Nick Flaherty
A key cybersecurity programme is on the brink of failure as a non-profit foundation aims to take over. The CVE (Common Vulnerability and Exposures) database, currently run by cybersecurity firm MITRE, has detailed potential vulnerabilities in hardware and software for systems around the world over the last 25 years.
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6 days ago |
ecinews.fr | Nick Flaherty |A Delapalisse
Actualités économiques | 18 avril 2025 Par Nick Flaherty, A Delapalisse IP Artisan Cadence Chiplets ARM vend son activité de propriété intellectuelle de la fondation Artisan, y compris son équipe d’ingénieurs, dans le cadre d’un changement fondamental. Le concepteur de cœurs de processeurs a toujours affirmé qu’il devait contrôler la propriété intellectuelle physique sous-jacente afin d’obtenir les meilleures performances pour ses conceptions de puces.
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6 days ago |
eenewseurope.com | Nick Flaherty
JEDEC Solid State Technology Association has published its standard for HMB4 high speed memory, doubling the channel count from 16 to 32 for higher performance. The JESD270-4 HBM4 brings higher bandwidth and larger stacks of higher capacity DRAM memory die to AI chips in particular. With transfer speeds up to 8 Gb/s across a 2048-bit interface, HBM4 boosts total bandwidth up to 2 TB/s with two pseudo-channels per channel.
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RT @eeNewsEurope: Tiny fanless Edge-AI IPC integrates Hailo-8 accelerators @solid_run @Hailo_ai #ai #edge #smart https://t.co/2fdJDFMDTv

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RT @eeNewsEurope: A methodology for turning an SoC into chiplets https://t.co/SXiV3qUKmr @Siemens @siemens_press https://t.co/UCyddtvHp0