Paul McLellan
Editor of Breakfast Bytes at Cadence Design Systems Blogs
Semiconductor, EDA, IP, lithography, embedded software, electronics, mobile. EDAgraffiti covers it all.
Articles
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Apr 18, 2024 |
edagraffiti.substack.com | Paul McLellan |Paul Mclellan
I first wrote about high-NA EUV back in 2022 in my post cleverly titled What is High NA EUV? The brief summary is that High NA EUV is the next generation of EUV creating even smaller features (and costing even more). High NA has a numerical aperture (NA) of 0.55 compared to 0.35 for the first generation…but if you don’t know what NA is then just know that bigger is better. You may know a few things about EUV which also apply to High NA EUV.
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Apr 3, 2024 |
edagraffiti.substack.com | Paul McLellan |Paul Mclellan
EDAgraffitiTechnology, EDA, semiconductor, and more. Everything from embedded software down to lithography. No thanks
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Jan 9, 2024 |
semiwiki.com | Paul McLellan |Paul Mclellan
The annual International Electron Devices Meeting (IEDM) took place last month. One of the presentations on the short course was by Matthew Metz of Intel titled New Materials Systems for Moore’s Law Continuation. In essence this was a look at some of the possibilities for what comes after silicon runs out of steam. Matthew started with a look at how the transistor has changed the world and, in particular, the materials innovations that have driven Intel’s own process roadmap over the decades.
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Dec 17, 2023 |
semiwiki.com | Paul McLellan |Paul Mclellan
I attended the recent International Electron Devices Meeting (IEDM) last week. Many of the sessions are too technical and too far away from high volume manufacture to make good topics for a blog post. As a Fellow from IBM said about 5nm at and earlier IEDM, “none of these ideas will impact 5nm. It takes ten years for a solution to from and IEDM paper to HVM. So 5nm will be something like FinFET with some sort of copper interconnect.” And so it turned out to be.
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Dec 10, 2023 |
semiwiki.com | Paul McLellan |Paul Mclellan
At the recent RISC-V Summit, the very last session was a panel about chiplets called Chiplets in the RISC-V Ecosystem. It was moderated by Calista Redmond, the CEO of RISC-V International. The panelists were:Laurent Moll, COO of ArterisAniket Saha, VP of Product Management of TenstorrentDale Greenley, VP of Engineering of Ventana MicrosystemsRob Aitken, Distinguished Architect of SynopsysThis is a slightly odd combination of topics to me.
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Today on #EDAgraffiti, 4 things you might not know about High NA EUV: Intel just bought the first one, someone else bought the second, ASML did 10nm patterning, and DP Low NA EUV may well be cheaper until the 2030s so maybe we don't need it yet https://t.co/HijddxYFu7
Do You Know What TFR Is? South Korea and Taiwan are the worst. Who will make our chips in the coming decades? https://t.co/G7nfodm5SV
Today's post on EDAgraffiti is about my AE stories...despite my never having been an AE. How I installed the design tools used for the first Arm processor. Plugging in a plotter. A trip to Moscow. https://t.co/FSCqgAhGyR