Tiera Oliver's profile photo

Tiera Oliver

Scottsdale

Associate Editor at Embedded Computing Design

Articles

  • 3 weeks ago | embeddedcomputing.com | Tiera Oliver

    News Arm announced the Zena CSS, the company's first pre-integrated and pre-validated platform for AI-defined vehicles built on Armv9 Automotive Enhanced (AE) technology.

  • 1 month ago | embeddedcomputing.com | Tiera Oliver

    News MINNEAPOLIS— Perforce Software is partnering with Siemens Digital Industries Software to transform how smart, connected products are designed and developed, reflecting a shared vision: the future of product innovation is software-defined, AI-powered, and silicon-enabled.

  • 1 month ago | embeddedcomputing.com | Tiera Oliver

    News SAN JOSE, Calif., and TAIPEI – Western Digital disaggregated storage and software-defined storage (SDS) for CSPs, enterprises, and STaaS providers. From massive-capacity, reliable JBODs (Just a Bunch of Disks) to ultra-fast EBOF (Ethernet Bunch of Flash) NVMe-oF disaggregated storage solutions for AI, the company’s Platforms Business delivers HDD- and SSD-based solutions designed to power today’s demanding workloads.

  • 1 month ago | embeddedcomputing.com | Tiera Oliver

    News TSMC, Cadence, KLA, Siemens, and Synopsys are advancing semiconductor manufacturing by adopting the NVIDIA CUDA-X and NVIDIA Blackwell platforms.   NVIDIA Blackwell GPUs, NVIDIA Grace CPUs, high-speed NVIDIA NVLink fabrics and switches, and domain-specific NVIDIA CUDA-X libraries like NVIDIA cuDSS and NVIDIA cuLitho are designed to improve computational lithography and device simulation for advanced chip manufacturing.

  • 1 month ago | embeddedcomputing.com | Tiera Oliver

    News RISC-V International has announced Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since June 2024, where he's helped to facilitate the technical vision of RISC-V International, working closely with RISC-V members around the globe to drive further adoption of the RISC-V Instruction Set Architecture (ISA).

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