Vasileia Georgiou

May 14, 2024 | nist.gov | William Borders |Advait Madhavan |Matthew Daniels |Vasileia Georgiou

, , , Vasileia Georgiou, Martin Lueker-Boden, Tiffany Santos, Patrick Braganca, , , The increasing scale of neural networks needed to support more complex applications has led to an increasing requirement for area- and energy-efficient hardware. One route to meeting the budget for these applications is to circumvent the von Neumann bottleneck by performing computation in or near memory.

May 14, 2024 | link.aps.org | William Borders |Advait Madhavan |Matthew Daniels |Vasileia Georgiou

The increasing scale of neural networks needed to support more complex applications has led to an increasing requirement for area- and energy-efficient hardware. One route to meeting the budget for these applications is to circumvent the von Neumann bottleneck by performing computation in or near memory. However, an inevitability of transferring neural networks onto hardware is the fact that nonidealities, such as device-to-device variations or poor device yield impact performance.