
Anne-Francoise Pele
Articles
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1 week ago |
eetimes.eu | Anne-Francoise Pele |Anne-Françoise Pelé
It’s been fifteen years since RISC-V turned the page on closed, proprietary ISAs and opened a new chapter in computing. Its open ISA allows the architecture to be adapted to different application domains, from performance to low-energy consumption and from safety to security. Speaking at the recent RISC-V Summit Europe 2025 in Paris, Thomas Dombek, head of Digital Integrated Circuits and Systems Department at CEA, looked back on seven years of involvement in the RISC-V ecosystem.
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2 weeks ago |
design-reuse-embedded.com | Anne-Francoise Pele |Anne-Françoise Pelé
Find the Latest SoC Solutionsfor... Automotive... IoT... Security... Audio... Video May. 19, 2025 – How to enhance AI compute with a scalable RISC-V NPU architecture By Anne-Françoise Pelé, EETimes Europe (May 15, 2025) In just two years, Semidynamics has “evolved from RISC-V with AI to AI with RISC-V”, Semidynamics’ chief sales officer Volker Politz said at this week’s RISC Summit Europe 2025 in Paris.
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2 weeks ago |
design-reuse.com | Anne-Francoise Pele |Anne-Françoise Pelé
May. 19, 2025, May. 19, 2025 – Emmanuel Till-Vattier, VP of Sales EMEA at Codasip, presented a brief product update at this week’s RISC-V Summit Europe 2025 in Paris.
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3 weeks ago |
eetimes.eu | Anne-Francoise Pele |Anne-Françoise Pelé
In a keynote speech at the RISC-V Summit Europe 2025 in Paris, Emmanuel Till-Vattier, VP of Sales EMEA at Codasip, presented a brief product update, including new possibilities for fast migration from Arm to RISC-V, new core customization features, and the latest advances in CHERI (Capability Hardware Enhanced RISC Instructions) memory protection. Codasip focuses on three goals, said Till-Vattier. “One is making RISC-V cores easy to customize. Two is making them safe.
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3 weeks ago |
eetimes.eu | Anne-Francoise Pele |Anne-Françoise Pelé
In just two years, Semidynamics has “evolved from RISC-V with AI to AI with RISC-V”, Semidynamics’ chief sales officer Volker Politz said at this week’s RISC Summit Europe 2025 in Paris. In 2023, the Barcelona, Spain-based startup came out of stealth mode with a family of fully customizable 64-bit RISC-V cores, designed to process large amounts of data for machine learning, artificial intelligence, and high-performance computing.
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