Anne-Françoise Pelé
Editor-in-Chief at EE Times EU
Correspondent at EE Times
EE Times Europe Editor-in-Chief EE Times Correspondent Ex-Content Manager for Google France
Articles
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2 weeks ago |
eetimes.eu | Anne-Francoise Pele |Anne-Françoise Pelé
Safety is non-negotiable in autonomous driving. Any failure or malfunction can cause accidents, resulting in serious injury or even death. More than ever, safety and security are interrelated priorities that will enable us to deliver on the promise of full autonomy at levels 4 and 5. In this issue, we explore the interdependence of safety and security in autonomous driving and the importance of establishing trust early in the design process.
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1 month ago |
eetimes.eu | Anne-Francoise Pele |Anne-Françoise Pelé
It’s been fifteen years since RISC-V turned the page on closed, proprietary ISAs and opened a new chapter in computing. Its open ISA allows the architecture to be adapted to different application domains, from performance to low-energy consumption and from safety to security. Speaking at the recent RISC-V Summit Europe 2025 in Paris, Thomas Dombek, head of Digital Integrated Circuits and Systems Department at CEA, looked back on seven years of involvement in the RISC-V ecosystem.
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1 month ago |
design-reuse-embedded.com | Anne-Francoise Pele |Anne-Françoise Pelé
Find the Latest SoC Solutionsfor... Automotive... IoT... Security... Audio... Video May. 19, 2025 – How to enhance AI compute with a scalable RISC-V NPU architecture By Anne-Françoise Pelé, EETimes Europe (May 15, 2025) In just two years, Semidynamics has “evolved from RISC-V with AI to AI with RISC-V”, Semidynamics’ chief sales officer Volker Politz said at this week’s RISC Summit Europe 2025 in Paris.
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1 month ago |
design-reuse.com | Anne-Francoise Pele |Anne-Françoise Pelé
May. 19, 2025, May. 19, 2025 – Emmanuel Till-Vattier, VP of Sales EMEA at Codasip, presented a brief product update at this week’s RISC-V Summit Europe 2025 in Paris.
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1 month ago |
eetimes.eu | Anne-Francoise Pele |Anne-Françoise Pelé
In a keynote speech at the RISC-V Summit Europe 2025 in Paris, Emmanuel Till-Vattier, VP of Sales EMEA at Codasip, presented a brief product update, including new possibilities for fast migration from Arm to RISC-V, new core customization features, and the latest advances in CHERI (Capability Hardware Enhanced RISC Instructions) memory protection. Codasip focuses on three goals, said Till-Vattier. “One is making RISC-V cores easy to customize. Two is making them safe.
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How to design #vehicle #computing platforms that are powerful, cost-effective and robust over time? At #ITFWorld2025, @EETimes_EU spoke to Bart Plackle, VP automotive @imec_int, about how #imec reimagines computing architectures for next-gen vehicles. https://t.co/c6i2chhBfv