Anne Meixner

Portland

Technical Editor at Semiconductor Engineering

Engineers' Daughter, semiconductor defects fascinate me, neuro-diversity advocate, engaging engineering presentations, ski instructor, engineer career coaching

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Articles

Who Is Most Likely To Link Financial And Manufacturing Data?

1 week ago | semiengineering.com | Anne Meixner

Experts at the Table: Semiconductor Engineering sat down to discuss which companies have the most to gain from linking financial data with manufacturing data analytics platforms with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, technical program manager and senior architect at Synopsys. What follows are excerpts of that conversation.
Hunting For Macro Defects

1 month ago | semiengineering.com | Anne Meixner

Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the wafer level, a macro-defect can affect more than one die, and in some cases large regions of a wafer. Finding macro defects can indicate a significant issue with a process module, a particular film, or wafer handling.
Need For KGD Drives Singulated Die Screening

1 month ago | semiengineering.com | Anne Meixner

The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly higher than with a single die. Better methods for inspecting and testing these devices are already starting to roll out. High-throughput infrared inspection is capable of catching more sub-surface defects that can cause device failure.
Cutting IC Manufacturing Costs By Combining Data

2 months ago | semiengineering.com | Anne Meixner

Experts at the Table: Semiconductor Engineering sat down to discuss the benefits of incorporating financial data into fab floor decision-making, including what kind of cost data is most useful, with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, technical program manager and senior architect at Synopsys. What follows are excerpts of that conversation.
IC Equipment Communication Standards Struggle As Data Volumes Grow

Feb 11, 2025 | semiengineering.com | Anne Meixner

The tsunami of data produced during wafer fabrication cannot be effectively leveraged without standards. They determine how data is accessed from equipment, which users need data access and when, and how fast it can be delivered. On top of that, best practices in data governance and data quality are needed to effectively interpret collected data and transfer results.
Screening For Known Good Interposers

Jan 14, 2025 | semiengineering.com | Anne Meixner

Ensuring the quality of silicon and organic interposers is becoming harder as the number of signals passing through them continues to grow, fueled by more chiplets, higher processing demands, and more layers of devices assembled in a package. Interposers initially were viewed as relatively simple conduits. That perception has changed rather dramatically in recent years with the growing focus on heterogeneous integration.
Aftermarket Sensors Boost Yield In Wafer Fabs

Dec 9, 2024 | semiengineering.com | Anne Meixner

Third-party sensors are being added into fab equipment to help boost yield and to extend the life of expensive tools, supplementing the sensors that come with equipment used in fabs. The data gleaned from those sensors has broad uses within the fab. It can measure process module performance, identify defect sources, and alert fabs of impending equipment failure. And when coupled with machine learning, the data from all sensors can improve process control and improve uptime.
Balancing Parallel Test Productivity With Yield & Cost

Nov 11, 2024 | semiengineering.com | Anne Meixner

Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantly reduce test time.
How Die Dimensions Challenge Assembly Processes

Sep 18, 2024 | semiengineering.com | Anne Meixner

Multi-die assemblies are becoming more common and more complex due to technology advancements and market demands, but differing die dimensions are making this process increasingly challenging. To fully enable a multi-chiplet ecosystem, standardized component handling and interfaces are needed. The underlying concept is similar to LEGO blocks that simply snap together, yet it’s nowhere near that simple.
Promises and Perils of Parallel Test

Sep 9, 2024 | semiengineering.com | Anne Meixner

Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance computing — but how much parallelism to add is not a straightforward formula.

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Anne Meixner @EngineersDaugh

10 Apr 25

Remembering @tmeixner this evening at a faith formation event, Roman Catholic. Hope was mentioned multiple times. I remembered that my brother' s posting of this quote was shared in the first family statement after his brutal murder. Crying has not been easy. Tears come now.