
Brian Bailey
Technology Editor at Semiconductor Engineering
ESL and Verification guru, author, blogger, photographer
Articles
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1 week ago |
semiengineering.com | Brian Bailey
The Design Automation Conference is approaching fast, and the evidence of a funding gap is in plain sight. An entire day of the technical conference has been dropped. This is disheartening to say the least, and in the long term it may be a very costly mistake. The problems started when the Internet bubble burst in 2000. Until then, DAC was growing to the point whereby few convention halls were large enough.
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1 week ago |
semiengineering.com | Brian Bailey
First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification since the dawn of the semiconductor age. When designs were small, this was a simple and effective method.
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3 weeks ago |
semiengineering.com | Brian Bailey
Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. Today, many companies have hit the reticle limit and are forced to move to multi-die solutions, but that does not create a plug-and-play chiplet market. These early systems do not need to adhere to standards to make them work, and they do not seek the same benefits.
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3 weeks ago |
chiplet-marketplace.com | Brian Bailey
A chiplet economy requires standards, organization, and tools — and that’s a problem. By Brian Bailey, Semi Engineering | May 15, 2025Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary.
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1 month ago |
semiengineering.com | Brian Bailey
Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to single tool or small flows provided by a single company. What is required is a digital twin of the development process itself on which AI can operate.
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Semiconductor Engineering .:. Gaps In The #Verification Flow https://t.co/s1zRVIBBkE Tools are struggling to keep up. #EDA #SemiEDA

Semiconductor Engineering .:. Can #Verification Meet In The Middle? https://t.co/yFxn2k8Qdo #EDA #SemiEDA

Semiconductor Engineering .:. FinFET Scaling Reaches Thermal Limit https://t.co/geAWOGiDK3 #EDA #SemiEDA #Semiconductor