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Brian Bailey

Portland

Technology Editor at Semiconductor Engineering

ESL and Verification guru, author, blogger, photographer

Articles

  • 18 hours ago | semiengineering.com | Brian Bailey

    Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. Today, many companies have hit the reticle limit and are forced to move to multi-die solutions, but that does not create a plug-and-play chiplet market. These early systems do not need to adhere to standards to make them work, and they do not seek the same benefits.

  • 22 hours ago | chiplet-marketplace.com | Brian Bailey

    A chiplet economy requires standards, organization, and tools — and that’s a problem. By Brian Bailey, Semi Engineering | May 15, 2025Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary.

  • 2 weeks ago | semiengineering.com | Brian Bailey

    Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to single tool or small flows provided by a single company. What is required is a digital twin of the development process itself on which AI can operate.

  • 3 weeks ago | semiengineering.com | Brian Bailey

    We live in an analog world, but analog has been minimized whenever possible. At some point digital and analog must come together in every electronic device, and that has long been an area where errors creep in. The Wilson Research Group and Siemens EDA functional verification study has long shown that analog and mixed signal are two of the highest causes of flaws that result in chip respins.

  • 3 weeks ago | semiengineering.com | Brian Bailey

    The headline numbers for the new Wilson Research/Siemens functional verification survey are out, and it shows a dramatic decline in the number of designs that are functionally correct and manufacturable. In the past year, that has dropped from 24% to just 14%. Along with that, there is a dramatic increase in the number of designs that are behind schedule, increasing from 67% to 75%.

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Brian Bailey
Brian Bailey @brian_esl
29 Sep 16

Semiconductor Engineering .:. Gaps In The #Verification Flow https://t.co/s1zRVIBBkE Tools are struggling to keep up. #EDA #SemiEDA

Brian Bailey
Brian Bailey @brian_esl
21 Jul 16

Semiconductor Engineering .:. Can #Verification Meet In The Middle? https://t.co/yFxn2k8Qdo #EDA #SemiEDA

Brian Bailey
Brian Bailey @brian_esl
12 May 16

Semiconductor Engineering .:. FinFET Scaling Reaches Thermal Limit https://t.co/geAWOGiDK3 #EDA #SemiEDA #Semiconductor