Bryon Moyer
Writer/Reporter at Semiconductor Engineering
Technology writer, engineer, manager, talking about cool technology especially in the Internet of Things, semiconductors, and design tools.
Articles
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1 week ago |
semiengineering.com | Bryon Moyer
Electrical interposers provide a convenient surface for mounting multiple chips within a single package, but even though interposer lines theoretically can be routed anywhere, insertion losses limit their practical length. Lines on interposers — and on silicon interposers in particular — can be exceedingly narrow. Having a small cross-section makes such lines resistive, degrading signals the farther they travel.
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2 weeks ago |
semiengineering.com | Bryon Moyer
Artificial intelligence (AI) involves intense computing and tons of data. The computing may be performed by CPUs, GPUs, or dedicated accelerators, and while the data travels through DRAM on its way to the processor, the best DRAM type for this purpose depends on the type of system that is performing the training or inference.
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1 month ago |
semiengineering.com | Bryon Moyer
Increasing levels of semiconductor integration means more work needs to be done in smaller spaces, which in turn generates more heat that needs to be dissipated. Managing heat dissipation in advanced node dies and in multi-die assemblies is critical to their functionality and their longevity. And while much of the focus has been on improving power efficiency, which reduces the rate of power growth, that alone is insufficient.
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1 month ago |
semiengineering.com | Bryon Moyer
UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. “It’s the blessing and the curse of UCIe,” said Mick Posner, senior product marketing group director at Cadence.
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1 month ago |
chiplet-marketplace.com | Bryon Moyer
Many features of UCIe 2.0 seen as “heavy” are optional, causing confusion. By Bryon Moyer, SemiEngineering | May 15, 2025UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion.
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RT @techinsightsinc: DSPs and DPUs! Cars, #5G, #cloud! Join Linley Gwennap as he moderates a session on specialized processors w/ @CEVA_IP,…
This week is about chips powering advanced driver-assist systems in newer cars. https://t.co/HlqwbQCWeE (Next week these should also come with a nicer picture too...) #adas #asild #asilb #automotive #automotivesoc #autonomousvehicles #renesas via @TechInsightsLGC
There's a new standard called UCIe for use in connecting chiplets within a package. https://t.co/6QVGDwtqUz #chiplets #interconnect #bunchofwires #odsa #ucie #pcie via @LinleyGroup