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Ed Sperling

Silicon Valley

Editor-in-Chief at Semiconductor Engineering

Editor In Chief of Semiconductor Engineering #semiconductor #semiEDA #AI #embedded #verification #lowpower #test #DataAnalytics #automotive #ICmanufacturing #ML

Articles

  • 2 days ago | chiplet-marketplace.com | Ed Sperling

    Multi-die assemblies enable more analog content, but that adds new security vulnerabilities for which there is little available research. By Ed Sperling, Semi Engineering | June 5, 2025The move toward multi-die assemblies and the increasing value of sensor data at the edge are beginning to focus attention and raise questions about security in analog circuits. In most SoC designs today, security is almost entirely a digital concern.

  • 2 days ago | semiengineering.com | Ed Sperling

    The move toward multi-die assemblies and the increasing value of sensor data at the edge are beginning to focus attention and raise questions about security in analog circuits. In most SoC designs today, security is almost entirely a digital concern. Security requirements in digital circuits are well understood, particularly in large data centers and at the upper end of edge computing, which are dominated by digital computing.

  • 1 week ago | chiplet-marketplace.com | Ed Sperling

    Trouble spots, and some solutions, for the next wave of high-performance semiconductors.

  • 1 week ago | semiengineering.com | Ed Sperling

    Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product management at Synopsys.

  • 1 week ago | semiengineering.com | Ed Sperling

    Home > Systems & Design > Optical Interconnectivity At 224 Gbps Pros and cons of replacing copper with optical in data-intensive AI systems.

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Ed Sperling
Ed Sperling @Chip_Insider
14 May 25

RT @SemiEngineering: New technical papers recently added to Semiconductor Engineering’s library: https://t.co/MnzGMnnWBP #semiconductor #D…

Ed Sperling
Ed Sperling @Chip_Insider
13 May 25

RT @SemiEngineering: Identifying Sources Of Silent Data Corruption https://t.co/mXEVOA4EIh

Ed Sperling
Ed Sperling @Chip_Insider
13 May 25

RT @SemiEngineering: E-Beam Inspection Proves Essential For Advanced Nodes https://t.co/MhLDgcOnnK