Ed Sperling

Silicon Valley

Editor-in-Chief at Semiconductor Engineering

Editor In Chief of Semiconductor Engineering #semiconductor #semiEDA #AI #embedded #verification #lowpower #test #DataAnalytics #automotive #ICmanufacturing #ML

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Articles

Conversing With Your Dishwasher

3 days ago | semiengineering.com | Ed Sperling

Home > Auto, Security & Pervasive Computing > Conversing With Your Dishwasher How on-device AI can improve interactions with machines. What does error 22 mean on your “smart” appliance? Today, most people have to look it up on the internet, but that’s about to change.
Three-Way Race To 3D-ICs

1 week ago | semiengineering.com | Ed Sperling

Intel Foundry, TSMC, and Samsung Foundry are scrambling to deliver all the foundational components of full 3D-ICs, which collectively will deliver orders of magnitude improvements in performance with minimal power sometime within the next few years. Much attention has been focused on process node advances, but a successful 3D-IC implementation is much more complex and comprehensive than just scaling digital logic.
Three-Way Race To 3D-ICs

1 week ago | chiplet-marketplace.com | Ed Sperling

Intel, TSMC, and Samsung are developing a broad set of technologies and relationships that will be required for the next generation of AI chips. By Ed Sperling, Semi Engineering | May 5th, 2025Intel Foundry, TSMC, and Samsung Foundry are scrambling to deliver all the foundational components of full 3D-ICs, which collectively will deliver orders of magnitude improvements in performance with minimal power sometime within the next few years.
AI Drives Re-Engineering Of Nearly Everything In Chips

3 weeks ago | semiengineering.com | Ed Sperling

AI’s ability to mine patterns across massive quantities of data is causing fundamental changes in how chips are used, how they are designed, and how they are packaged and built. These shifts are especially apparent in high-performance AI architectures being used inside of large data centers, where chiplets are being deployed to process, move, and store massive amounts of data.
Secure Handling Of Financial Data In Manufacturing

3 weeks ago | semiengineering.com | Ed Sperling

Experts at the Table: Semiconductor Engineering sat down to discuss the advantages associated with linking financial data with manufacturing data analytic platforms, real security challenges and the best uses for AI/ML methods, with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, technical program manager and senior architect at Synopsys.
What's Changing In SerDes

4 weeks ago | semiengineering.com | Ed Sperling

Home > Systems & Design > What’s Changing In SerDes Faster data movement in AI systems comes at a cost. SerDes is all about pushing data through the smallest number of physical channels. But when it comes to AI, more data needs to be moved, and it has to be moved more quickly.
Benefits And Challenges In Multi-Die Assemblies

1 month ago | semiengineering.com | Ed Sperling |Laura Peters

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of this discussion, click here. Part two is here.
Benefits And Challenges In Multi-Die Assemblies

1 month ago | chiplet-marketplace.com | Ed Sperling |Laura Peters

What makes advanced packaging so attractive to some companies and not others. By Ed Sperling And Laura Peters, SemiEngineering | April 2nd, 2025Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion.
First-Time Silicon Success Plummets

1 month ago | semiengineering.com | Ed Sperling

First-time silicon success is falling sharply due to rising complexity, the need for more iterations as chipmakers shift from monolithic chips to multi-die assemblies, and an increasing amount of customization that makes design and verification more time-consuming. Details from a new functional verification survey[1] highlight the growing difficulty of developing advanced chips that are both functional and reliable.
Chip Failures: Prevention And Responses Over Time

1 month ago | semiengineering.com | Ed Sperling

Experts at the Table: Semiconductor Engineering sat down to discuss the causes of chip failures, how to respond to them, and how that can change over time, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, high-tech solutions product manager at Ansys. What follows are excerpts of that conversation.