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5 days ago | 
semiengineering.com | Gregory Haley
Home > Home > On The Ground At ECTC 2025 Inside Chips Podcast: Much more efficient computing, faster interconnects, and panel-level packaging.
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1 week ago | 
semiengineering.com | Gregory Haley
Home > Home > Inside Chips Podcast: May 27 News and insights from imec ITF World 2025. Jo De Boeck, chief strategy officer and EVP at imec, talks with Semiconductor Engineering Technology Editor Gregory Haley about system technology co-optimization and the intersection of technology and AI.
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2 weeks ago | 
semiengineering.com | Gregory Haley
Experts at the Table: As leading-edge lithography nodes push further into EUV and beyond, mask-making has become one of the most critical and costly aspects of semiconductor manufacturing. At the same time, non-EUV applications are stretching the lifetime of older tools and processes, challenging the industry to find new solutions for both ends of the spectrum.
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1 month ago | 
semiengineering.com | Gregory Haley
Electron-beam inspection is proving to be indispensable for finding critical defects at sub-5nm dimensions. The challenge now is how to speed up the process to make it economically palatable to fabs. E-beam inspection’s notorious sensitivity-throughput tradeoff has made comprehensive defect coverage with e-beam at these advanced nodes especially problematic.
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1 month ago | 
semiengineering.com | Gregory Haley
As packaging complexity increases and nodes shrink, defect detection becomes significantly more difficult. Engineers must contend with subtle variations introduced during fabrication and assembly without sacrificing throughput. New material stacks degrade signal-to-noise ratios, which makes metrology more difficult.
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1 month ago | 
semiengineering.com | Gregory Haley
Advanced packaging has evolved far beyond the simple stacking of dies and connecting of interposers. Once a passive conduit between silicon and the outside world, it has become an active component of overall device performance.
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2 months ago | 
semiengineering.com | Gregory Haley
Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against the complexity of modern chip architectures.
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2 months ago | 
semiengineering.com | Gregory Haley
Interposers and substrates are undergoing a profound transformation from intermediaries to engineered platforms responsible for power distribution, thermal management, high-density interconnects, and signal integrity in the most advanced computing systems. This shift is being driven by AI, high-performance computing (HPC), and next-generation communications, where the need for heterogeneous integration is pushing the limits of packaging technologies.
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2 months ago | 
chiplet-marketplace.com | Gregory Haley
New materials and processes will help with power distribution and thermal dissipation in advanced packages. By Gregory Haley, Semi Engineering | March 24th, 2025Interposers and substrates are undergoing a profound transformation from intermediaries to engineered platforms responsible for power distribution, thermal management, high-density interconnects, and signal integrity in the most advanced computing systems.
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2 months ago | 
semiengineering.com | Gregory Haley
Failure analysis (FA) is an essential step for achieving sufficient yield in semiconductor manufacturing, but it’s struggling to keep pace with smaller dimensions, advanced packaging, and new power delivery architectures. All of these developments make defects harder to find and more expensive to fix, which impacts the reliability of chips and systems.
