Liz Allan

1 week ago | semiengineering.com | Liz Allan

Mission-critical hardware used in space is not supposed to fail at all, because lives may be lost in addition to resources, availability, performance, and budgets. For space applications, failure can occur due to a range of factors, including the weather on the day of launch, human error, environmental conditions, unexpected or unknown hazards and degradation of parts to chemical factors, aging, and radiation.

2 weeks ago | semiengineering.com | Liz Allan

Aerospace safety requirements and standards vary depending on whether a spacecraft is manned or unmanned, and how crucial the mission is. The defense contractors designing these spacecraft take various approaches to functional safety based on how critical a component is for the mission to succeed. While losing a few images during an Earth-bound observation may not matter, losing a satellite can be a major setback. And absolutely nobody wants to lose a jet or a rocket.

1 month ago | semiengineering.com | Liz Allan

Chips destined for the skies or armed forces need extra everything. They require higher layers of abstraction to simulate all the moving parts in the field, high-reliability testing for harsh environments, in addition to system-level test. They also need radiation-hardening and ceramic materials for space, extra safety layers, and advanced security techniques. As in the automotive sector, the safety-critical designation means lives are at risk.

2 months ago | semiengineering.com | Liz Allan

The sensing and processing technology used in smart phones, watches, and rings is starting to be being deployed in a wide variety of wearable devices, ranging from those that fill the gap between sports and med tech, to haptic devices to assist the visually impaired and AR/VR glasses. Emerging applications include payment, building, and factory wearables. Most of these devices process signals, then plug into AI and ML tools to analyze the data at the edge, on a phone, or in the cloud.

2 months ago | semiengineering.com | Liz Allan

Chip Industry Technical Paper Roundup: Feb. 25 NVM-CIM accelerators; AI HW energy; TSV faults; Si/SiGe multi-layer stacks; BPR to suppress substrate leakage in CFETs; small-pitch interconnects; DRAM read disturbance; HW-aligned sparse attention architecture.