Chris Edwards

1 week ago | cacm.acm.org | Chris Edwards |Orit Hazzan |Micah Beck

The computer scientists of the 1960s had high hopes for the way humans and intelligent machines would work with each other. In separate essays that date back more than half a century, Joseph Licklider and Douglas Engelbart described situations where the humans and artificial intelligence (AI) would exchange ideas in insightful dialogues of the kind followed by ancient Greek philosophers. Some of that optimism has not gone away.

Jul 30, 2024 | cacm.acm.org | Chris Edwards |Sam Greengard |Shaoshan Liu |Jeremy Roschelle

Humble rust may provide the key to a new generation of low-power computing devices and memories. Its properties could overcome some of the problems of today’s attempts to harness magnetic fields for spintronic systems. Electron spin, the source of magnetic fields, could prove a far more energy-efficient way to process data than today’s charge-based circuits currently dominated by silicon technology. Aside from the read-write heads in disk drives, however, progress in spintronics has been slow.

May 29, 2024 | techdesignforums.com | Chris Edwards

By Chris Edwards |  No Comments  |  Posted: May 29, 2024 Topics/Categories: Blog - IP  |  Tags: 3DIC, bonded wafers, silicon photonics, wafer bonding | Organizations: IMEC Imec is presenting at this weel’s IEEE Electronic Components and Technology Conference (ECTC) a die-to-wafer bonding process that can reduce the bond-pad pitch to 2µm with an overlay error of less than 350nm.

May 12, 2024 | techdesignforums.com | Chris Edwards

By Chris Edwards |  No Comments  |  Posted: May 13, 2024 Topics/Categories: Blog - EDA, Embedded  |  Tags: 3DIC, advanced packaging, AI, HPC, IoT, sensor hub | Organizations: IBM, IEEE, Intel Foundry Services, KAIST This year’s Electronic Components and Technology Conference (ECTC), held in Denver at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.

May 1, 2024 | techdesignforums.com | Chris Edwards

By Chris Edwards | No Comments | Posted: May 2, 2024 Topics/Categories: Blog - EDA, IP | Tags: 3nm, backside power delivery, finFET, monolithic 3DIC, power analysis | Organizations: IMEC, Intel, Samsung Electronics Intel will describe its 3nm-node finFET process at the VLSI Symposium on Technology and Circuits in Hawaii in mid-June alongside papers from a variety of semiconductor organisations that investigate the viability of backside contacts and power distribution, and novel memory...