Laura Peters

Chicago

Executive Editor at Semiconductor Engineering

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Articles

Identifying Sources Of Silent Data Corruption

1 week ago | semiengineering.com | Laura Peters

Silent data errors are raising concerns in large data centers, where they can propagate through systems and wreak havoc on long-duration programs like AI training runs. SDEs, also called silent data corruption, are technically rare. But with many thousands of servers, which contain millions of processors running at high utilization rates, these damaging events become common in large fleets.
Backside Power Delivery Nears Production

4 weeks ago | semiengineering.com | Laura Peters

Backside power delivery is being called a game changer — a breakthrough technology and the next great enabler in CMOS scaling. It promises significant PPA advances, including faster switching, lower voltage droop, and reduced power supply noise. And it is poised to deliver these benefits below the 2nm node, despite a substantial disruption in front-end processes from lithography pattern distortion caused by extreme wafer thinning, wafer bonding, and multi-layer process stacks on the frontside.
Why Thin Film Measurements Matter

1 month ago | semiengineering.com | Laura Peters

Semiconductor devices are becoming thinner and more complex, making thin deposited films even harder to measure and control. With 3nm node devices in production and 2nm nodes ramping toward first-silicon, the importance of precise film measurement is only growing in significance as fabs seek to maintain the performance and reliability of leading-edge devices.
Benefits And Challenges In Multi-Die Assemblies

1 month ago | semiengineering.com | Ed Sperling |Laura Peters

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of this discussion, click here. Part two is here.
Benefits And Challenges In Multi-Die Assemblies

1 month ago | chiplet-marketplace.com | Ed Sperling |Laura Peters

What makes advanced packaging so attractive to some companies and not others. By Ed Sperling And Laura Peters, SemiEngineering | April 2nd, 2025Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion.
The Rise Of Thin Wafer Processing

1 month ago | semiengineering.com | Laura Peters

The shift from planar SoCs to 3D-ICs and advanced packages requires much thinner wafers in order to improve performance and reduce power, reducing the distance that signals need to travel and the amount of energy needed to drive them. Markets calling for ultrathin wafers are growing. The combined thickness of an HBM module with 12 DRAM dies and a base logic chip is still less than that of a prime silicon wafer.
Automation And AI Improve Failure Analysis

2 months ago | semiengineering.com | Laura Peters

When a chip malfunctions it’s the job of the failure analysis engineer to determine how it failed or significantly deviated from its key performance metrics. The cost of failure in the field can be huge in terms of downtime, recalls, damage to a company’s reputation, and more. For these reasons, chipmakers take customer returns very seriously, focusing resources to quickly get to the bottom of the failure’s root cause in dedicated FA labs.
Interconnects Approach Tipping Point

2 months ago | semiengineering.com | Laura Peters

As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip’s RC delay. Changing this dynamic requires a superior conductor, particularly at 18nm metal pitch, to better transfer signals and power efficiently.
What's Next In Advanced Packaging?

2 months ago | semiengineering.com | Ed Sperling |Laura Peters

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC progress and issues, photonics, and tradeoffs with different interposers and bridge technologies, with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of this discussion, click here.
What’s Next In Advanced Packaging?

2 months ago | chiplet-marketplace.com | Ed Sperling |Laura Peters

Momentum is building for organic interposers, 3D stacking, and photonics, but questions remain about how the industry gets there and what kinds of tradeoffs will be necessary.